Boost Valley is the right choice to provide functional verification for your digital IC design.
When working on a SoC or IP development it is imperative that strong expertise as well as a high quality verification strategy both exist. Having both, we guarantee the success of your ASIC design on silicon avoiding the penalties of high respin costs.
Architecture and implementation of verification environment
Building a thorough Verification Plan & Test Plan
Building state-of-the-art test benches using HVL (System Verilog - OVM / UVM – VHDL – Verilog )
Directed, Constraint Random and Transaction level Testing
Performance measurement tests
Assertions and coverage reports
Smoke-test, mini-regressions and exhaustive regressions
Verification IP Development and Integration
Test system build and verification management
Pre-silicon validation through FPGA prototyping
UVM Verification environment for 22Gbps Optical Transceiver.
- Verification plan for both sub-modules and top level
- VIPs for sub modules, unit level test benches, and top level test bench
- Functional coverage metrics and reports
- Code coverage reports
- Test cases generation and running regression
- Formal verification
- Post APR verification
UVM Verification environment for Floating point MAC unit compatible with IEEE754 single precision format.
UVM Sequences Tested implementation of multiplier and adder both having 3 pipelined stages – covering all Multiplier and Adder functionalities separately and combined
Reusable Processor UVM Verification Environment for open source Wishbone Bus Z80 Processor
Processor is SOC designed for Altera DE1 development board and the Diligent Spartan 3E, and provide access to leds, switches, buttons, IO pins, SRAM, VGA, LCD and keyboard using Z80 assembly language. Generic UVM environment to test all supported features for Z80 Processor – coverage reports .
Publication: “Reusable Processor Verification Methodology Based on UVM” in DVCon Conference Oct, 2014.
UVM Verification environment for Inter-IC Sound (I2S) – 2000 Gates
Publication: “Case Study: Comparison between Conventional VHDL and UVM Test-Benches for a Slave I2S Transceiver”